• DocumentCode
    1792370
  • Title

    Power network-on-chip for scalable power delivery

  • Author

    Vaisband, Inna ; Friedman, Eby G.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Rochester, Rochester, NY, USA
  • fYear
    2014
  • fDate
    1-1 June 2014
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    Delivering high quality power to the on-chip circuitry with minimum energy loss is an essential component of integrated circuits. The quality of the power supply can be efficiently addressed with multiple power supplies and decoupling capacitors integrated on-chip close to the points-of-load. Distributed power delivery requires the co-design of hundreds of power converters with thousands of decoupling capacitors and billions of current loads within multiple power domains, significantly increasing the design complexity of existing power delivery systems. Efficient real-time management of the power budget in these complicated distributed power delivery systems is impractical with existing ad hoc approaches. The concept of a power network on-chip (PNoC) is introduced here as a systematic methodological solution for on-chip power delivery and management that provides enhanced power control and real-time management of resource sharing. A PNoC with four power domains is investigated based on the proposed architecture, and circuits for sensing, routing, and dynamic control of the on-chip power are described. The built-in modularity of the PNoC is exploited to apply dynamic voltage scaling, illustrating the scalability of the PNoC platform, while exhibiting power savings of up to 32%.
  • Keywords
    capacitors; network-on-chip; power convertors; power supply circuits; PNoC; decoupling capacitors; design complexity; distributed power delivery systems; dynamic voltage scaling; on-chip power delivery; power budget; power control; power converters; power network-on-chip; power supply; real time management; Capacitors; Complexity theory; Network-on-chip; Power supplies; Regulators; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System Level Interconnect Prediction (SLIP), 2014 ACM/IEEE International Workshop on
  • Conference_Location
    San Francisco, CA
  • Type

    conf

  • DOI
    10.1145/2633948.2633949
  • Filename
    6886038