DocumentCode :
1792544
Title :
Low temperature wafer bonding for wafer-level 3D integration
Author :
Dragoi, Viorel ; Rebhan, B. ; Burggraf, Jurgen ; Razek, N.
Author_Institution :
EV Group, St. Florian am Inn, Austria
fYear :
2014
fDate :
15-16 July 2014
Firstpage :
9
Lastpage :
9
Abstract :
This work presents new results on low temperature wafer bonding processes. Low temperature Cu-Cu thermo-compression bonding was successfully performed at process temperatures lower than 200°C. A process flow was developed for stacking thin Si wafers (<;25 μm) using a combination of temporary bonding with rigid carrier and plasma activated wafer bonding. Together with high accuracy optical alignment technology the two processes can be used to address the needs of manufacturing processes based on TSV technology.
Keywords :
copper; cryogenic electronics; lead bonding; plasma materials processing; three-dimensional integrated circuits; wafer bonding; wafer level packaging; Cu; Si; TSV technology; low temperature Cu-Cu thermocompression bonding; low temperature wafer bonding processes; plasma activated wafer bonding; process flow; rigid carrier; thin silicon wafers; wafer-level 3D integration; Bonding; Plasma temperature; Silicon; Stacking; Three-dimensional displays; Wafer bonding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Temperature Bonding for 3D Integration (LTB-3D), 2014 4th IEEE International Workshop on
Conference_Location :
Tokyo
Print_ISBN :
978-1-4799-5260-1
Type :
conf
DOI :
10.1109/LTB-3D.2014.6886148
Filename :
6886148
Link To Document :
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