Towards a black-box methodology for SRAM stability analysis

SRAM stability analysis has become a primary issue in the design of memories. While the classic definition of static noise margin based on butterfly curves was once enough to determine SRAM stability and properly size the transistors of a 6T bitcell, the recent trends of technology and supply voltage scaling have caused SRAM yield to decrease significantly. As a result, more complex methodologies for stability analysis have been suggested in the form of dynamic noise margins. In this paper, a brief review of static and dynamic analysis methods is given, along with the advantages and disadvantages of each approach. Ultimately, a combination of these approaches should lead to the development of a complete toolkit for stability analysis in the deep-nanoscale era.