Designing of single precision floating point DSP co-processor

In this paper, we show that using FPGA as a CoProcessor with floating point arithmetic can enhance DSP system performance levels through optimized core implementation of critical compute-intensive digital signal processing algorithms such as Fast Fourier Transform (FFT). Our approach is based on building basic building blocks, by implementing optimized, multi-cycle, floating point arithmetic core, which are then used to implement much complex layers of logic such as FFT butterfly, complex multiplier and a DFT block. We present performance results to show that a speedup of 10-19X can be achieved over an optimized FFT DSP Coprocessor implementation on a low cost FPGA such as Cyclone IV.