Title :
A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors
Author :
Maniotis, P. ; Fitsios, D. ; Kanellos, G.T. ; Pleros, N.
Author_Institution :
Dept. of Inf., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece
Abstract :
We demonstrate a novel 16GHz physical layer optical cache memory architecture for the 2-way set associative cache mapping scheme. Both memory addresses and optical words are WDM-formatted while physical layer simulations demonstrate successful Read/Write operation.
Keywords :
cache storage; memory architecture; microprocessor chips; optical storage; WDM-format; chip multiprocessors; frequency 16 GHz; memory addresses; optical words; physical layer optical cache memory architecture; physical layer simulations; read-write operation; set associative cache mapping scheme; Cache memory; Computer architecture; High-speed optical techniques; Optical buffering; Optical interconnections; Optical wavelength conversion; Random access memory;
Conference_Titel :
Optical Fiber Communications Conference and Exhibition (OFC), 2014
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-5575-2994-7
DOI :
10.1364/OFC.2014.Th2A.6
