Title :
A novel chip-multiprocessor architecture with optically interconnected shared L1 optical cache memory
Author :
Maniotis, P. ; Gitzenis, S. ; Tassiulas, L. ; Pleros, N.
Author_Institution :
Dept. of Inf., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece
Abstract :
We demonstrate a system-level CMP architecture where optical cache memories are shared among multiple processing cores through optical buses. System-level simulations show 25-45% execution time improvement and significant capacity requirements reduction through simpler memory hierarchy.
Keywords :
cache storage; multiprocessing systems; optical interconnections; optical storage; capacity requirements; chip-multiprocessor architecture; execution time improvement; multiple processing cores; optical buses; optical interconnection; shared L1 optical cache memory; system-level simulations; Benchmark testing; Cache memory; Computer architecture; High-speed optical techniques; Optical interconnections; Optical waveguides; Simulation;
Conference_Titel :
Optical Fiber Communications Conference and Exhibition (OFC), 2014
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-5575-2994-7
DOI :
10.1364/OFC.2014.W2A.60
