• DocumentCode
    1793855
  • Title

    Reducing the power consumption of the CMA equalizer update for a digital coherent receiver

  • Author

    Cardenas, Daniel ; Lavery, Domanic ; Watts, Philip ; Savory, Seb J.

  • Author_Institution
    Dept. of Electron. & Electr. Eng., Univ. Coll. London, London, UK
  • fYear
    2014
  • fDate
    9-13 March 2014
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    A reduced complexity multiplier-free CMA equalizer update is proposed and synthesized for a 10 Gb/s receiver using a 45-nm CMOS process. The proposed algorithm allows up to 52% power consumption reduction without penalty in performance.
  • Keywords
    CMOS analogue integrated circuits; equalisers; integrated optics; optical receivers; CMOS process; bit rate 10 Gbit/s; constant modulus algorithm; digital coherent receiver; power consumption reduction; reduced complexity multiplier-free CMA equalizer update; size 45 nm; Algorithm design and analysis; Complexity theory; Equalizers; Hardware; Optical filters; Power demand; Receivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Optical Fiber Communications Conference and Exhibition (OFC), 2014
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    978-1-5575-2994-7
  • Type

    conf

  • DOI
    10.1364/OFC.2014.Th4D.5
  • Filename
    6886835
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1793855