Simplified partially parallel DVB-S2 LDPC decoder architectural design based on FPGA

In this paper, a simplified partially parallel decoder architectural based on field programmable gate array (FPGA) devices for Digital Video Broadcasting-Satellite 2 low-density parity-check(DVB-S2-LDPC) codes has been presented. We introduce the current research status about decoder design for LDPC code and described the motivation of this paper in the first part. Then, we present the simulating results on parameter selection and architectural design. The primary contribution of this paper is summarized as follows: firstly, we proposed a novel and more efficient barrel shifter design. secondly, we optimized sub-modules architecture including: Bit Node Update, Check Node Update and combined and flexible data storage strategy so that this decoder can achieve both high data throughput and low resource-on-chip consumption.