DocumentCode :
1796822
Title :
SpinNNaker: The world´s biggest NoC
Author :
Furber, Steve
Author_Institution :
Univ. of Manchester, Manchester, UK
fYear :
2014
fDate :
17-19 Sept. 2014
Abstract :
The SpiNNaker (Spiking Neural Network Architecture) project will soon deliver a machine incorporating a million ARM processor cores for real-time modelling of large-scale spiking neural networks. Although the scale of the machine is in the realms of high-performance computing, the technology used to build the machine comes very much from the mobile embedded world, using small integer cores and Network-on-Chip communications both on and between chips. The full machine will use a total of 10 square meters of active silicon area with 57,600 routers using predominantly multicast algorithms to convey real- time spike information through a lightweight asynchronous packet-switched fabric. In this talk I will focus on the NoC aspects, including novel approaches to fault-tolerance and deadlock avoidance.
Keywords :
fault tolerance; integrated circuit modelling; microprocessor chips; network routing; network-on-chip; neural net architecture; silicon; ARM processor cores; NoC; Si; SpinNNaker project; asynchronous packet-switched fabric; deadlock avoidance; fault-tolerance; integer cores; multicast algorithms; network-on-chip communications; silicon area; size 10 m; spike information; spiking neural network architecture; Abstracts; Biological neural networks; Computer architecture; Computers; Educational institutions; Modeling; Real-time systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Networks-on-Chip (NoCS), 2014 Eighth IEEE/ACM International Symposium on
Conference_Location :
Ferrara
Type :
conf
DOI :
10.1109/NOCS.2014.7008754
Filename :
7008754
Link To Document :
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