Transient queuing models for input-buffered routers in Network-on-Chip

Analytical modeling of Network-on-Chip mainly focuses on steady-state conditions although traffic patterns and the behavior of applications are frequently non-stationary. Hence, in such scenarios, it is likely that a system seldom reaches stationarity, and steady-state models are inapplicable. In this work, we propose queuing-theoretic models for the transient analysis of output contention in Network-on-Chip. Contention occurs when multiple input queues intend to forward to the same output, and it is one of the main reasons for increased latencies and blocking probabilities in input-buffered routers. In Network-on-Chip, the end-to-end latency of a single packet can be determined by adding the latencies along its path. Therefore, understanding interactions within a single router are beneficial for system and parameter design of Network-on-Chip. Furthermore, we validate the models proposed by numerical evaluations which confirm the accuracy and practicality of the queuing models.