Technology assessment of silicon interposers for manycore SoCs: Active, passive, or optical?

In this paper, the influence of the possible silicon interposer 2.5D stacking strategies on the micro-architecture of an interconnect topology is studied. We present case studies at different chip scales, based on active CMOS interposers using synchronous or asynchronous NoCs or point to point links, passive metal interposers with DC lines or RF microstrip lines, and optical interposers using multipoint links. We show that a single physical link energy per bit is not a sufficient metric to benchmark these strategies, as the choice leads to strong implications on various parts of the system, including clock distribution, data synchronization between blocks, arbitration for shared resources in the network or at network boundaries, tuning of the optical devices on laser wavelengths, and thermal management at different granularity levels, from photonic devices to chip. Based on a system-level integration analysis, we identify trends on the best candidate depending on bandwidth requirements and number of stacked dies.