Title :
DyAFNoC: Characterization and analysis of a dynamically reconfigurable NoC using a DOR-based deadlock-free routing algorithm
Author :
Villegas Castillo, Ernesto ; Miorandi, Gabriele ; Wang Jiang Chau
Author_Institution :
Electron. Syst. Dept., Univ. of Sao Paulo, Sao Paulo, Brazil
Abstract :
Several simulations have been performed in order to verify the system architecture behavior, showing that the dynamic reconfiguration time overhead is mainly due to the packet draining time. The synthesis results obtained a maximum frequency of 182.02MHz (Virtex 4) and 162.86MHz (Virtex 6) for both 5×5 and 8×8 meshes respectively. Table I shows the synthesis results for a 5-port 16-bit router and MRCS logic for a 5×5 mesh.
Keywords :
network routing; network-on-chip; DOR; DyAFNoC; MRCS logic; deadlock-free routing algorithm; dynamically reconfigurable NoC; frequency 162.86 MHz; frequency 182.02 MHz; packet draining time; storage capacity 16 bit; Heuristic algorithms; Network topology; Ports (Computers); Routing; System recovery; System-on-chip; Topology;
Conference_Titel :
Networks-on-Chip (NoCS), 2014 Eighth IEEE/ACM International Symposium on
Conference_Location :
Ferrara
DOI :
10.1109/NOCS.2014.7008788
