Title :
A sub-threshold to super-threshold Level Conversion Flip Flop for sub/near-threshold dual-supply operation
Author :
Chao Wang ; Jun Zhou ; Xin Liu ; Annamalai, Arasu Muthukumaraswamy ; Minkyu Je
Author_Institution :
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
Abstract :
This paper presents a novel Current-Mirror (CM) based Master-Slave Level Conversion Flip Flop (MS-LCFF) to perform data latching and level shifting from sub-threshold voltage, to near-threshold voltage, and up to super-threshold voltage. The CM-based MS-LCFF enables energy-efficient ultra-low-voltage operation by applying dual-supply and multi-supply designs into sub/near-threshold regions. Simulation results show that with a 0.18-μm technology the proposed LCFF is able to conduct data latching and level shifting from 0.3 V to 0.5 V, and up to 1.8 V, with performance improved by 8×, power consumption decreased by 3×, and silicon area reduced by 13.3% over the conventional method, when performing conversion from 0.3 V to 0.5 V. The measurement results of applying the proposed LCFF-based dual-supply operation to a sub-threshold FIR filter operating at 300 kHz demonstrate that a 21.8% power reduction can be achieved without performance loss by dual-supply operation at 0.3V and 0.5V, compared to the single-supply operation at 0.5V.
Keywords :
FIR filters; current mirrors; energy conservation; flip-flops; integrated circuit design; logic design; low-power electronics; silicon; CM-based MS-LCFF; LCFF-based dual-supply operation; Si; current mirror; data latching; dual-supply designs; energy efficiency; frequency 300 kHz; level shifting; master-slave level conversion flip flop; multisupply designs; near-threshold dual-supply operation; near-threshold voltage; power consumption; power reduction; silicon area; size 0.18 mum; subthreshold FIR filter; subthreshold dual-supply operation; subthreshold level conversion flip flop; subthreshold voltage; super-threshold level conversion flip flop; super-threshold voltage; voltage 0.3 V to 0.5 V; Clocks; Delays; Energy efficiency; Finite impulse response filters; Latches; MOS devices; Robustness;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
DOI :
10.1109/ASSCC.2014.7008855