Title :
A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS
Author :
Yao-Sheng Hu ; Chi-Huai Shih ; Hung-Yen Tai ; Hung-Wei Chen ; Hsin-Shu Chen
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A 0.6V 10-bit 150MS/s single-channel asynchronous subranging SAR ADC using a settling-time relief technique is presented. The technique extends the allocated DAC settling time with the assistance of a coarse ADC and minimizes digital loop delay so that it can reach high speed and low power at a 0.6V supply. This ADC consumes 0.264mW at 150MS/s in 40nm CMOS technology. It achieves an SNDR of 50.5dB at Nyquist rate and results in an FoM of 6.4fJ/c.-s. The core circuit only occupies an area of 0.0063 mm2.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; asynchronous circuits; low-power electronics; CMOS technology; Nyquist rate; conversion-step subranging SAR; digital loop delay; power 0.264 mW; settling-time relief technique; single-channel asynchronous subranging SAR ADC; size 40 nm; voltage 0.6 V; word length 10 bit; CMOS integrated circuits; Capacitors; Delays; Noise; Redundancy; Switches; Analog to digital converter (ADC); settling time; subranging; successive approximation register (SAR);
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
DOI :
10.1109/ASSCC.2014.7008865
