Title :
A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS
Author :
Shih-Hao Huang ; Zheng-Hao Hung ; Wei-Zen Chen
Author_Institution :
Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
This paper describes a single-chip, 2 × 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1:4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 μApp at bit-error-rate of less than 10-12. Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm2.
Keywords :
CMOS integrated circuits; demultiplexing equipment; optical receivers; photodetectors; ALPD current-sensing scheme; alternating photodetector current-sensing scheme; bit rate 20 Gbit/s; bulk CMOS technology; correlation-based timing recovery; demultiplexer; digital comparator; front-end receiver; single-chip time-interleaved integrating-type optical receiver; size 40 nm; CMOS integrated circuits; Capacitors; Optical receivers; Partial discharges; Sensitivity; Timing; Monolithic optical receiver; comparator; high-density optical interconnect; photodetector (PD);
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
DOI :
10.1109/ASSCC.2014.7008869
