Title :
Energy efficient computing in nanoscale CMOS: Challenges and opportunities
Author_Institution :
Intel Labs., USA
Abstract :
Future computing systems spanning exascale supercomputers to wearable devices demand orders of magnitude improvements in energy efficiency while providing desired performance. The system-on-chip (SoC) designs need to span a wide range of performance and power across diverse platforms and workloads. The designs must achieve robust near-threshold-voltage (NTV) operation in nanoscale CMOS process while supporting a wide voltage-frequency operating range with minimal impact on die cost. Circuit and design technologies need to overcome the challenges posed by device parameter variations, supply noises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations.
Keywords :
CMOS digital integrated circuits; integrated circuit design; integrated circuit reliability; system-on-chip; SoC designs; activity changes; aging-induced degradations; device parameter variations; energy efficient computing; exascale supercomputers; excursions; magnitude improvements; nanoscale CMOS; nanoscale CMOS process; reliability considerations; supply noises; system-on-chip designs; temperature; voltage-frequency operating range; wearable devices; workload; CMOS integrated circuits; Energy efficiency; Noise; Robustness; System-on-chip; Temperature sensors; Voltage control; CMOS; NTV; SoC; energy efficiency; power management; variations;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
DOI :
10.1109/ASSCC.2014.7008875
