Title :
0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS
Author :
Po-Tsang Huang ; Shu-Lin Lai ; Ching-Te Chuang ; Wei Hwang ; Huang, Jie ; Hu, Anping ; Kan, Paul ; Jia, Mingming ; Lv, Kimi ; Zhang, Boming
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this paper, a 256×40 energy-efficient ternary content addressable memory (TCAM) macro is designed and implemented in 40nm low power (LP) CMOS. Due to the thicker gate oxide in LP process, a 16T TCAM cell with p-type comparison circuits is proposed to increase the Ion/Ioff difference of the dynamic circuitry. To further improve energy efficiency, don´t-care-based ripple search-lines/bit-lines are used to reduce both the switching activities and wire capacitance. Moreover, column-based data-aware power control is employed for leakage power reduction and write-ability improvements. The experimental results show a leakage power reduction of 28.9%, a search-line power reduction of 31.74% and an energy efficiency metric of the TCAM macro of 0.339 fJ/bit/search.
Keywords :
CMOS memory circuits; energy conservation; integrated circuit design; low-power electronics; power control; LP CMOS; LP process; TCAM cell; TCAM macrodesign; column-based data-aware power control; don´t-care-based ripple bit-lines; don´t-care-based ripple search-lines; energy efficiency; gate oxide; leakage power reduction; low power CMOS; p-type comparison circuits; search-line power reduction; size 40 nm; ternary content addressable memory; wire capacitance; write-ability improvements; CMOS integrated circuits; CMOS process; Capacitance; Delays; Energy efficiency; Logic gates; Switches; Embedded memory; TCAM; energy-efficient;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
DOI :
10.1109/ASSCC.2014.7008877
