Title :
A 4.9 mW neural network task scheduler for congestion-minimized network-on-chip in multi-core systems
Author :
Youchang Kim ; Gyeonghoon Kim ; Injoon Hong ; Donghyun Kim ; Hoi-Jun Yoo
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST) Daejeon, Daejeon, South Korea
Abstract :
A neural network task scheduler (NNTS) is proposed for the congestion-minimized network-on-chip in multi-core systems. The NNTS is composed of a near-optimal task assignment (NOTA) algorithm and a reconfigurable precision neural network accelerator (RP-NNA). The NOTA adopting a neural network is proposed to predict and avoid the network congestion intelligently. And the RP-NNA is implemented to improve the throughput of NOTA with dynamically adjustable precision. In the case that the NNTS is integrated into a NoC-based multi-core SoC for the augmented reality applications, 79.2% prediction accuracy of NoC communication pattern is achieved and the overall latency is reduced by 24.4%. As a result, the RP-NNA consumes only 4.9 mW and improves the energy efficiency of system by 22.7%.
Keywords :
augmented reality; multiprocessing systems; network-on-chip; neural nets; power aware computing; processor scheduling; NNTS; NOTA; NoC communication pattern; NoC-based multicore SoC; RP-NNA; augmented reality applications; congestion-minimized network-on-chip; energy efficiency; multicore systems; near-optimal task assignment algorithm; network congestion; neural network task scheduler; power 4.9 mW; reconfigurable precision neural network accelerator; Accuracy; Artificial neural networks; Neurons; Piecewise linear approximation; System-on-chip; Throughput; network congestion; network-on-chip (NoC); neural network (NN); task assignment;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
DOI :
10.1109/ASSCC.2014.7008898
