Title :
A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI
Author :
Narayanan, Aravind Tharayil ; Wei Deng ; Dongsheng Yang ; Rui Wu ; Okada, Kenichi ; Matsuzawa, Akira
Author_Institution :
Dept. of Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan
Abstract :
This paper presents a fully-synthesizable clock and data recovery circuit using injection locking technique. The challenges presented by automated place and route for high speed applications is overcome using background calibration mechanism. The fully-synthesizable all-digital architecture presented in this work is fabricated in 28nm FDSOI technology. The system has a top data-rate of 10.05Gb/s while consuming 16mW power from 1.0V supply.
Keywords :
calibration; clock and data recovery circuits; network synthesis; silicon-on-insulator; FDSOI technology; PVT-robust fully-synthesizable CDR; automated place; automated route; background calibration mechanism; bit rate 10.05 Gbit/s; clock and data recovery circuit; fully-synthesizable all-digital architecture; high speed applications; injection locking technique; power 16 mW; size 28 nm; voltage 1.0 V; CMOS integrated circuits; Calibration; Clocks; Frequency locked loops; Jitter; Oscillators; Radiation detectors;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
DOI :
10.1109/ASSCC.2014.7008916
