Title :
A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit
Author :
Li-Hung Chiueh ; Tai-Cheng Lee
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
An adaptive circuit is proposed to adjust CDR loop bandwidth based on different jitter spectral profile for better jitter performance. The preventional lock detector (PLD) is employed to achieve better jitter suppression ability without jitter tolerance (JTOL) degradation. The proposed circuit enhances the jitter suppression by 14.14 dB at an 8-MHz sinusoidal jitter source. This adaptive block is fully-digital synthesized and the whole circuit consumes 86.4 mW for a 6-Gb/s input data.
Keywords :
clock and data recovery circuits; jitter; network synthesis; CDR loop bandwidth; PLD; adaptive block; adaptive-loop-bandwidth clock and data recovery circuit; bit rate 6 Gbit/s; jitter spectral profile; jitter suppression ability; power 86.4 mW; preventional lock detector; sinusoidal jitter source; Bandwidth; Clocks; Detectors; Jitter; Noise; Tracking loops; Voltage-controlled oscillators; adaptive loop bandwidth; jitter suppression; jitter tolerance;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
DOI :
10.1109/ASSCC.2014.7008917
