A 5.2mW IEEE 802.15.6 HBC standard compatible transceiver with power efficient delay-locked-loop based BPSK demodulator

A low power fully IEEE 802.15.6 HBC compatible transceiver is implemented in 0.13μm CMOS process. The transmitter uses an analog active filter instead of digital type filter to remove the power-hungry high speed DAC and clock generation. In the receiver, a power-efficient delay-locked-loop (DLL) based BPSK demodulator is adopted to relax the stability problem of synchronization feedback loop. The sample and hold operation in the control voltage of the DLL enables the receiver to turn off the synchronization circuits during the hold time, leading to over 30% power reduction. The energy detection ability with Received Signal Strength Indicator (RSSI) detector for MAC operation adjusts the operating mode of LNA and even reconfigures the receiver architecture for power-efficient operation, resulting in over 70% power saving. As a result, the proposed transceiver can fully satisfy the HBC standard while consuming 4.3mA from the 1.2V supply.