An efficient interpolation filter VLSI architecture for HEVC standard

The emerging video coding standard, High Efficient Video Coding (HEVC), aims at doubling coding efficiency of H.264/AVC. Fractional Motion Estimation (FME) in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40% of the total encoding time and its high computational complexity. Firstly, this paper proposes a fast interpolation filter algorithm, which is based on the 8-pixel interpolation unit. It can save 9.9% processing time on average while introducing only 0.1256% BD_PSNR coding quality degradation. Based on this, the paper designs and realizes the interpolation filter VLSI architecture with the reconfigurable configuration and the cell block reuse to reduce the implement hardware area. The final VLSI implementation only requires 64.5k gates in a standard 90nm CMOS technology at an operating frequency of 193MHz. The proposed architecture can be reused for half-pixel interpolation and quarter-pixel interpolation, which can reduce the area cost for about 131040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 3840×2160@47fps video sequences.