A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology

A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBΩ transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10^-12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors´ knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm² including pad.