Title :
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS
Author :
Chun-Yuan Cheng ; Jinn-Shyan Wang ; Pei-Yuan Chou ; Shiou-Ching Chen ; Chi-Tien Sun ; Yuan-Hua Chu ; Tzu-Yi Yang
Author_Institution :
Dept. of EE & SoC/AIM-HI Centers, Nat. Chung Cheng Univ., Chiayi, Taiwan
Abstract :
It is challenging to design a closed-loop all-digital delay-locked loop (ADDLL) that also has a small area, low power, and fast locking for a wide frequency range operation. In this work a cyclic half-delay-line architecture with the same type of delay lines for cyclic delay deduction and coarse locking is proposed to achieve the design goals of small area and fast locking for a wide frequency range operation. In addition to clock gating, which is used to reduce power consumption in the lock-in state regardless of the clock frequency, automatic bypassing of the cyclic operation is developed to reduce power consumption for high-frequency operations. Based on these proposed techniques, a 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 closed-loop ADDLL is realized in 65-nm CMOS.
Keywords :
CMOS digital integrated circuits; clocks; delay lock loops; integrated circuit design; low-power electronics; power consumption; CMOS; all-digital delay-locked loop; automatic bypassing; clock frequency; clock gating; closed-loop ADDLL; coarse locking; cyclic delay deduction; cyclic half-delay-line architecture; frequency 3 MHz to 1.8 GHz; power 94 muW to 9.5 mW; power consumption; size 0.0153 mm; size 65 nm; CMOS integrated circuits; Clocks; Delay lines; Delays; Jitter; Power demand; Radiation detectors; ADDLL; low power; small area; wide range;
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2014 IEEE Asian
Conference_Location :
KaoHsiung
Print_ISBN :
978-1-4799-4090-5
DOI :
10.1109/ASSCC.2014.7008935
