Title :
On-board snubber circuit for damping of anti-resonance peak in total PDN
Author :
Yamaguchi, Toru ; Kurita, Kanae ; Sudo, Toshio
Author_Institution :
Shibaura Inst. of Technol., Tokyo, Japan
Abstract :
Power supply noise is a serious issue for advanced CMOS LSIs and systems, since the performance of LSI chip is becoming more sensitive to power supply fluctuation under the lower power supply voltage. Because power supply noises are strongly related to the anti-resonance peak frequency in the total power distribution network (PDN), suppressing the anti-resonance peak is one of the most important design concerns. In this paper, the on-board snubber circuits (RC series circuits) has been studied to suppress the anti-resonance peak. The optimal circuit parameters of the on-board snubber circuits such as capacitance (Csnb) and resistance (Rdmp) were derived for quad flat package (QFP) and ball grid array (BGA) to effectively suppress the anti-resonance peak of the total PDN impedance. As a result, the settling time of power supply noises were greatly decreased. Furthermore, clock frequency dependency of power supply noise was also significantly decreased.
Keywords :
CMOS integrated circuits; RC circuits; ball grid arrays; circuit optimisation; integrated circuit interconnections; integrated circuit noise; integrated circuit packaging; snubbers; CMOS integrated circuit; RC series circuits; antiresonance peak damping; antiresonance peak frequency; ball grid array; on-board snubber circuits; optimal circuit parameters; power supply noise; quad flat package; total PDN; total power distribution network; Capacitors; Damping; Impedance; Integrated circuit modeling; Noise; Power supplies; Snubbers;
Conference_Titel :
CPMT Symposium Japan (ICSJ), 2014 IEEE
Conference_Location :
Kyoto
Print_ISBN :
978-1-4799-6194-8
DOI :
10.1109/ICSJ.2014.7009617
