Fabrication and electrical characterization of Parylene-HT liner bottom-up copper filled through silicon via (TSV)

Author

Bui Thanh Tung ; Xiaojin Cheng ; Watanabe, N. ; Kato, Fumiki ; Kikuchi, Kazuro ; Aoyagi, Masahiro

Author_Institution

Nanoelectron. Res. Inst., Nat. Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan

fYear

2014

fDate

4-6 Nov. 2014

Firstpage

154

Lastpage

157

Abstract

In this study, Parylene-HT, the newest commercially available parylene with the lowest dielectric constant and highest temperature tolerance within all the series, was investigated as insulation/liner in the application of through-silicon-via (TSV). Bottom-up copper filled TSV with 1 μm Parylene-HT insulator was realized on a 100 μm-thick Si wafer through via etching, parylene vapor deposition, and electroplating processes. The fabrication process on the 36 μm diameter TSVs, are reported here, as well as their electrical properties, including DC leakage and capacitance.

Keywords

copper; electric properties; electroplating; etching; integrated circuit manufacture; organic insulating materials; permittivity; polymers; silicon; three-dimensional integrated circuits; vapour deposition; Cu; DC leakage; Si; TSV; bottom-up copper filled through silicon via; dielectric constant; electrical characterization; electrical properties; electroplating processes; insulation; parylene vapor deposition; parylene-HT insulator; parylene-HT liner; size 1 mum; size 100 mum; size 3 mum; temperature tolerance; through via etching; Capacitance; Copper; Fabrication; Insulators; Silicon; Substrates; Through-silicon vias; Parylene-HT; TSV; TSV liner; bottom-up copper filled; electroplating;

fLanguage

English

Publisher

ieee

Conference_Titel

CPMT Symposium Japan (ICSJ), 2014 IEEE

Conference_Location

Kyoto

Print_ISBN

978-1-4799-6194-8

Type

conf

DOI

10.1109/ICSJ.2014.7009633

Filename

7009633