A computational architecture for discrete wavelet transform using lifting scheme

The Discrete Wavelet Transform (DWT) is an important technique for signal analysis, compressing and denoising due to its excellent locality in the time-frequency domain. The DWT is developed by convolutions which demand both a large number of mathematical operations and a large amount of storage. The lifting scheme reduces both computational and storage requirements. We have developed a computational architecture for inverse DWT using the lifting scheme. The design was developed in VHDL and then implemented into a Virtex 5 FPGA. We aim to reach a high throughput and reduce the design area. The architecture takes 3L + N(1-0.5^L) clock cycles to compute L levels of 1D reconstruction for data of size N. Some comparisons suggest that our work could be faster than previous works.