A synthesizable digitally controlled oscillator with only standard cells: A 810 to 1400 MHz digital back-end design flow compatible design with PVT calibration

Author

Balcioglu, Yalcin ; Dundar, Gunhan

Author_Institution

Electr. & Electron. Eng. Dept., Bogazici Univ., Istanbul, Turkey

fYear

2014

fDate

14-15 Nov. 2014

Firstpage

1

Lastpage

4

Abstract

A novel Digitally Controlled Oscillator (DCO) architecture adjusting driving strength rather than capacitance for coarse and fine tuning in ring oscillator architectures has been proposed with full digital design flow as part of an effort to fully digitize All Digital Phase Locked Loops (ADPLL). Targeted for automotive wired applications, the design favors portability and flexibility first then area, power and noise performance.

Keywords

calibration; digital phase locked loops; logic design; PVT calibration; all digital phase locked loops; automotive wired applications; digital back-end design flow compatible design; driving strength; frequency 810 MHz to 1400 MHz; full digital design flow; ring oscillator architectures; standard cells; synthesizable digitally controlled oscillator; Calibration; Clocks; Delays; Oscillators; Phase locked loops; Standards; Tuning; All Digital Phase Locked Loop; Digitally Controlled Oscillator;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics and Telecommunications (ISETC), 2014 11th International Symposium on

Conference_Location

Timisoara

Print_ISBN

978-1-4799-7266-1

Type

conf

DOI

10.1109/ISETC.2014.7010733

Filename

7010733