DocumentCode
1799896
Title
SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers
Author
Yunqi Zhang ; Laurenzano, Michael A. ; Mars, Jason ; Lingjia Tang
Author_Institution
Adv. Comput. Archit. Lab., Univ. of Michigan, Ann Arbor, MI, USA
fYear
2014
fDate
13-17 Dec. 2014
Firstpage
406
Lastpage
418
Abstract
One of the key challenges for improving efficiency in warehouse scale computers (WSCs) is to improve server utilization while guaranteeing the quality of service (QoS) of latency-sensitive applications. To this end, prior work has proposed techniques to precisely predict performance and QoS interference to identify ´safe´ application co-locations. However, such techniques are only applicable to resources shared across cores. Achieving such precise interference prediction on real-system simultaneous multithreading (SMT) architectures has been a significantly challenging open problem due to the complexity introduced by sharing resources within a core. In this paper, we demonstrate through a real-system investigation that the fundamental difference between resource sharing behaviors on CMP and SMT architectures calls for a redesign of the way we model interference. For SMT servers, the interference on different shared resources, including private caches, memory ports, as well as integer and floating-point functional units, do not correlate with each other. This insight suggests the necessity of decoupling interference into multiple resource sharing dimensions. In this work, we propose SMiTe, a methodology that enables precise performance prediction for SMT co-location on real-system commodity processors. With a set of Rulers, which are carefully designed software stressors that apply pressure to a multidimensional space of shared resources, we quantify application sensitivity and contentiousness in a decoupled manner. We then establish a regression model to combine the sensitivity and contentiousness in different dimensions to predict performance interference. Using this methodology, we are able to precisely predict the performance interference in SMT co-location with an average error of 2.80% on SPEC CPU2006 and 1.79% on Cloud Suite. Our evaluation shows that SMiTe allows us to improve the utilization of WSCs by up to 42.57% while enforcing an application´s QoS re- uirements.
Keywords
computer centres; multi-threading; quality of service; regression analysis; shared memory systems; CMP; CloudSuite; QoS prediction; Rulers; SMT architectures; SMT co-location; SMiTe; SPEC CPU2006; WSCs; application contentiousness; application sensitivity; chip multiprocessor; performance interference; quality of service; real-system SMT processors; real-system commodity processors; regression model; resource sharing behaviors; shared resource multidimensional space; simultaneous multithreading; software stressors; warehouse scale computers; Degradation; Interference; Multicore processing; Program processors; Quality of service; Sensitivity; Servers; datacenter; quality of service; simultaneous multithreading; warehouse scale computer;
fLanguage
English
Publisher
ieee
Conference_Titel
Microarchitecture (MICRO), 2014 47th Annual IEEE/ACM International Symposium on
Conference_Location
Cambridge
ISSN
1072-4451
Type
conf
DOI
10.1109/MICRO.2014.53
Filename
7011405
Link To Document