Power-delay trade-offs in SCL gates

In this paper the analysis of source-coupled logic (SCL) logic gates in terms of speed performance and its trade-off with power dissipation is discussed. In particular, an analytical model of noise margin and delay is derived and then used to optimally design SCL circuits for assigned requirements. The delay model is simple enough to provide the necessary intuitive understanding of the power-delay trade-off. Simple design equations are developed to size design parameters in different cases, either when high performance or an optimum balance with power dissipation is needed. Due to the analytical approach, the strategies discussed are suitable for pencil-and-paper calculations and avoid simulation iterations during design.