LT-PRPG: Power minimization technique for test-per-scan BIST

This paper presents a new low transition pseudo- random pattern generator (LT-PRPG) for test-per-scan built-in self-test (BIST) applications. The proposed LT-PRPG is composed of a LFSR and a 2times1 multiplexer. When used to generate test patterns for test-per-scan BIST, it reduces the number of transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the circuit- under-test (CUT) during the test application. Various properties of the proposed LT-PRPG and the methodology of the design are presented in this paper. Experimental results for the ISCAS´89 benchmark circuits show that the proposed design can reduce the switching activity by 36% to 47% with a negligible effect on the fault coverage.