New directions in interconnect performance optimization

It is now admitted that interconnects represent a bottleneck for delay, power consumption and area on chips. To face these problems some works have been realized around performance optimizations. However results, presented in this paper, show that optimization techniques do not always face good criteria for interconnect performance optimizations. We therefore have developed a high-level estimation tool based on transistor-level characterizations, which provides users fast and precise results for time and power consumption estimation. Estimation results allowed us to determine a new interconnect consumption model and also enabled to find some new key issues that have to be pointed out for future performance optimizations.