MOSFET aspect ratio optimization for minimized transistor mismatch at UDSM technology nodes

In this paper, we provide a comparative estimation of the W/L aspect ratio required to obtain a symmetric behavior of n-channel and p-channel MOS devices across ultradeep submicron (UDSM) technology nodes and various supply voltage ranges. This symmetric behavior is in terms of matching propagation delay during the pull-up (pMOS dependent) and pull-down (nMOS dependent) output transitions. To achieve this, mismatch in drain currents as well as threshold voltages for both devices is minimized through W/L ratio optimization, incorporating realistic variations from expected values. In doing so, significant deviations are observed in pMOS W/L ratio from the conventional values of 2-2.5 for obtaining identical transistor strength to nMOS in terms of on current. The ratio is seen to range from 1.3× to as high as 8.6× for superthreshold and subthreshold regimes respectively, depending on the specific technology node in use. Moreover, threshold voltages are matched for both devices through suitable sizing of channel lengths upto 1.09× to improve overall transistor matching. The optimal W/L values thus obtained can be suitably used for pre-design optimization depending on the choice of technology and supply voltage range.