VLSI architecture of digital matched filter and prime interleaver for W-CDMA

Author

Uchida, Yoshihiro ; Ise, Masanao ; Onoye, Takao ; Shirakawa, Isao ; Arungsrisangchai, Itthichai

Author_Institution

Dept. Inf. Sys. Eng, Osaka Univ., Japan

Volume

3

fYear

2002

fDate

2002

Abstract

A VLSI architecture dedicated to W-CDMA (Wideband Code Division Multiple Access) baseband modem is described, with the main theme focused on the cell searcher and PIL (Prime InterLeaver). A search algorithm is refined for the cell searcher to minimize the circuit size, maintaining the operating throughput. In addition, a time-shared scheme is adopted for the turbo encoding/decoding, aiming at the maximization of the hardware sharing in the encoding/decoding process. Finally, implementation results are shown to demonstrate that the proposed architecture can contribute much toward the practical low-power implementation of W-CDMA baseband modem LSI.

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; code division multiple access; decoding; digital filters; digital radio; digital signal processing chips; low-power electronics; matched filters; mobile radio; telecommunication computing; turbo codes; 100 MHz; VLSI architecture; W-CDMA baseband modem; cell searcher; digital matched filter; hardware sharing; low-power implementation; modem LSI; operating throughput; prime interleaver; search algorithm; time-shared scheme; turbo encoding/decoding; wideband CDMA; wideband code division multiple access; Baseband; Circuits; Decoding; Encoding; Matched filters; Modems; Multiaccess communication; Throughput; Very large scale integration; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010212

Filename

1010212