Peak power reduction method for Between-Core Vector Overlapping Testing

Author

Suzuki, Wataru ; Shinogi, Tsuyoshi ; Hayashi, Terumine ; Kawanaka, Hiroharu ; Tsuruoka, Shinji

Author_Institution

Dept. of Electr. & Electron. Eng., Mie Univ., Tsu

fYear

2008

fDate

25-27 March 2008

Firstpage

1

Lastpage

6

Abstract

A parallel core testing method, between-core vector overlapping testing, has been proposed for manufacturing testing of SoCs consisting of multiple cores. The testing method uses a test data sequence generated by overlapping the test vectors for the constituent cores, and tests the cores in parallel by the test data sequence. This method needs only a small number of LSI input pins for testing and performs the testing efficiently. However, test power problem has not been considered yet. In this paper we address the peak power problem in testing.

Keywords

integrated circuit testing; large scale integration; low-power electronics; system-on-chip; between-core vector overlapping testing; large scale integration; manufacturing testing; parallel core testing method; peak power problem; peak power reduction method; system-on-chip; test data sequence; Circuit faults; Circuit testing; Costs; Electronic equipment testing; Large scale integration; Manufacturing; Pins; Power dissipation; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Technology of Integrated Systems in Nanoscale Era, 2008. DTIS 2008. 3rd International Conference on

Conference_Location

Tozeur

Print_ISBN

978-1-4244-1576-2

Electronic_ISBN

978-1-4244-1577-9

Type

conf

DOI

10.1109/DTIS.2008.4540231

Filename

4540231