A Smart Card Power Analysis Simulator

Side-channel attacks are a great threat to cryptographic algorithms embedded in microcontrollers. This paper proposes a software environment devoted to the analysis of resistance of cryptographic algorithms implementations against differential power attacks. Our method consists in generating execution traces and computing abstractions of these traces at different levels, on the basis on classical consumption models. In particular this allows the user to isolate some parts of its implementation in order to analyze information leakages directly linked to them. The advantage of this environment is twofold. Firstly, it produces precise and differential analysis of a cryptographic algorithm resistance to side-channel attacks. Secondly, it replaces the use of the testbed in the first development stages thus improving the global design process for resistant implementations by making easier interactions between development and validation. To other extends, the design of the simulator relies on a functional style, opening the way to formal proofs of resistance.