Title :
An efficient architecture for accumulator-based test generation of SIC pairs
Author :
Voyiatzis, I. ; Efstathiou, C.
Author_Institution :
Technol. Educ. Inst. of Athens, Athens
Abstract :
The detection of robustly detectable sequential faults has been extensively studied. A number of researchers have provided theoretical as well as experimental results designating that the application of single input change (SIC) pairs of test patterns is favorable for sequential fault testing. In this paper a novel implementation for the generation of SIC pairs is presented. The proposed implementation is based on Ling adders that are utilized in current data paths due to their high speed of operation. Since the timing characteristics of the adder are not modified, the presented architecture provides a practical solution for the built-in testing of circuits that contain such adders.
Keywords :
adders; built-in self test; integrated circuit testing; sequential circuits; timing circuits; Ling adders; accumulator-based test generation; built-in testing; circuit testing; sequential fault testing; single input change pairs; timing; Adders; Built-in self-test; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Microwave integrated circuits; Sequential analysis; Silicon carbide; BIST; Delay Fault Testing; Ling Adders; Stuck-Open Testing; Two-Pattern Testing;
Conference_Titel :
Design and Technology of Integrated Systems in Nanoscale Era, 2008. DTIS 2008. 3rd International Conference on
Conference_Location :
Tozeur
Print_ISBN :
978-1-4244-1576-2
Electronic_ISBN :
978-1-4244-1577-9
DOI :
10.1109/DTIS.2008.4540235
