DocumentCode :
1800657
Title :
On reducing aliasing in accumulator-based compaction
Author :
Voyiatzis, I.
Author_Institution :
Dept. of Inf., Technol. Educ. Inst. of Athens, Athens
fYear :
2008
fDate :
25-27 March 2008
Firstpage :
1
Lastpage :
12
Abstract :
The utilization of accumulators for time compaction of the responses in built-in self test environments has been studied by various researchers. One of the well-known problems of time compactors is aliasing, i.e. the event that a series of responses containing errors result in a signature equal to that of an error-free response sequence. In this paper we propose a scheme to reduce aliasing in accumulator based compaction environments. With the proposed scheme, the aliasing probability tends to zero, as the number of the patterns of the test set increases.
Keywords :
automatic test pattern generation; built-in self test; compaction; probability; accumulator-based compaction; aliasing probability; aliasing reduction; built-in self test environments; error-free response sequence; time compaction; Adders; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Educational technology; Integrated circuit testing; Monitoring; Test pattern generators; Accumulator-based compaction; Built-In Self Test; aliasing probability; time compaction;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Technology of Integrated Systems in Nanoscale Era, 2008. DTIS 2008. 3rd International Conference on
Conference_Location :
Tozeur
Print_ISBN :
978-1-4244-1576-2
Electronic_ISBN :
978-1-4244-1577-9
Type :
conf
DOI :
10.1109/DTIS.2008.4540237
Filename :
4540237
Link To Document :
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