Low power design of a decimation filter in multi-stand standard receiver

This work deals with low-power design of a decimation filter used in a wireless multi-standard receiver. We propose a solution that reduces the dynamic power consumption by reducing the filtering activity. This solution uses the clock-gating technique on parallel filters combined with appropriate clock distribution. We optimize the arithmetic operators to save area with the power consumption and increase the operating frequency. The new design saves about thirty percent of consumed power compared to a solution using only the clock-gating technique.