Logic synthesis for PLA with 2-input logic elements

In this paper, we present a new logic synthesis method for PLA with 2-input logic elements. A PLA with 2-input logic elements can achieve low-power dissipation and high-speed operation by using latch sense-amplifiers and a charge sharing scheme. In addition, an arbitrary 2-input logic function is conveniently implemented in place of the conventional AND/OR planes. Therefore it can realize some classes of logic functions in a smaller circuit area. Since the proposed method makes full use of the existing multiple-valued logic minimization algorithms along with a new logic extraction technique for 2-input functions, it can be easily implemented and can handle practical circuits. The method has been implemented and the experimental results are presented.