Dependability consequences of fault-tolerant technique integrated in stack processor emulator using information flow approach

Nowadays, electronic systems are becoming increasingly attractive for many applications. Such systems should be more and more dependable and require the evaluation and the improvement of their dependability parameters. In the continuity of the CETIM project [1], the principal objective is to define an integrated design of dependable mechatronic systems. In addition, the presence of programmable electronics imposes the existence of hardware/software interactions for the evaluation of dependability parameters. In this work we apply the informational flow approach [2] to evaluate some dependability parameters of a stack processor architecture in order to make adjustment during the co-design step. A VHDL- RTL modeling of the processor instruction set is done in order to carry on the information flow modeling. The probability of existence on different functional mode is estimated and discussed for 2 instructions. The first study concerns the instruction models without taking into account a fault-tolerant method. The second study concerns the same models but with taking into account this fault-tolerant method.