Fundamental switching frequency optimal pulsewidth modulation of medium voltage cascaded seven-level inverter

Multilevel converters are now popular power electronic converters for medium-voltage high power drives. The switching losses dominate in the high power drives and hence, low device switching frequencies are preferred to improve the overall efficiency of drive system. However, low device switching frequencies leads to increase in total harmonic distortion (THD) of stator currents. One emerging technique for low switching frequency operation of multilevel converters without compromising on THD of stator currents is synchronous optimal pulsewidth modulation (SOP). The goal of our study was to propose a new SOP technique for a cascaded seven-level inverter such that maximum device switching frequencies are limited to rated fundamental frequency (50/60 Hz) and all power semiconductor devices operate at same switching frequency. The off-line optimal pulse patterns were determined for seven-level inverter assuming steady-state operation. Then, switching angles for each semiconductor device were determined and stored in a FPGA controller. A low power prototype of seven-level cascade inverter has been developed to demonstrate the proposed SOP technique. The experimental results illustrated that proposed SOP technique was able to maintain the quality of stator currents, while device switching frequencies were limited to rated fundamental frequency.