Generation of memory architecture in operator design methodology

Nowadays, traditional ASIC design methodology shows its limitations to meet the short time-to-market which is the hallmark of modern consumer electronic products, and great interests have been focused on high-level synthesis (HLS) in the past two decades. In this paper, the scheme for generation of the memory architecture in a novel HLS method named operator design methodology is proposed. The principle and process of operator design methodology is first presented, then the steps of mapping the data array and pointer in C description to the memory model in hardware description is demonstrated, finally a hardware implementation of a target algorithm is conducted based on the proposed memory generation scheme and the experiment results is compared with that of the SPARK tool by UC San Diego, which presents an 65% increase in the performance and 30% reduction in hardware cost under the constraint of 100MHz clock frequency.