Design guidelines for reducing the impact of metal interference structures on the performance on-chip antennas

The increase in the operating frequency and the projected die size to 2.4/spl times/2.4 cm/sup 2/ for CMOS circuits has led to a feasibility study for wireless interconnection utilizing microwaves within ICs with integrated antennas for distributing high frequency signals (O, K.K. et al., GOMAC, p.306-9, 1999). A possible use is for clock distribution. The power transmission gain and phase of the antenna pair (between the transmitting antenna and the receiving antenna) are key factors determining the feasibility of the whole system. A serious concern is that metal structures, such as bus lines or power lines, near an antenna can act as interference structures and significantly affect the on-chip antenna characteristics, such as the gain, phase, and S/sub 11/. To study the effects of metal structures on antennas, a test chip with various metal interference structures was fabricated using a three metal layer process. Based on evaluation of the structures, a set of design guidelines for reducing the impact of the structures to gain and S/sub 11/ has been developed. Additionally, use of an aluminum nitride (AlN) propagating layer under a silicon wafer to improve antenna pair gain in the presence of interference structures is also investigated.