DocumentCode :
1801408
Title :
The design and implementation of DSP TMS320C40 parallel processing system
Author :
Baoli, Wang ; Changli, Li ; Dinghua, Guan
Author_Institution :
Inst. of Acoust., Acad. Sinica, Beijing, China
Volume :
1
fYear :
1996
fDate :
14-18 Oct 1996
Firstpage :
453
Abstract :
This paper presents the design and implementation of four C40 based parallel processing system. It is comprised of four single CPU ISA-bus board. All four C40s are fully connected together through comports. The supporting software include basic tools such as simulator, assembler, linker, C compiler, parallel run-time support library. Four CPU debug/monitor software was also developed to ease programming. As an example, parallel FFT has been implemented using the system. Under the control of an IBM-PC, the system peak performance is 200 MFLOPS and can be further expanded. It is suitable for radar, sonar, image signal processing
Keywords :
digital signal processing chips; fast Fourier transforms; floating point arithmetic; image processing; parallel architectures; radar signal processing; sonar signal processing; 200 MFLOPS; C compiler; CPU ISA-bus board; CPU debug/monitor software; DSP TMS320C40 parallel processing system; IBM-PC; assembler; image signal processing; linker; parallel FFT; parallel run-time support library; performance; programming; radar signal processing; simulator; software; sonar signal processing; Assembly; Control systems; Digital signal processing; Monitoring; Parallel processing; Radar signal processing; Runtime library; Software debugging; Software libraries; Software tools;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing, 1996., 3rd International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-2912-0
Type :
conf
DOI :
10.1109/ICSIGP.1996.567300
Filename :
567300
Link To Document :
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