Design and Implementation of Adaptive Equalizer Based On FPGA

The hardware design of LMS algorithm is implemented via using hardware description language VHDL and FPGA. First, adaptive parameters are obtained via the simulation of LMS-based adaptive equalizer on MATLAB platform. Second, the data, processed by FPGA, such as step size, input and output signals, desired signals, and coefficients of equalizer, is strictly expressed into the fixed-point number. Third, according to the function of the module, the system structure of FPGA-based LMS algorithm is divided into data storage module, state control module, output computation module, error adjustment module, and weight update module, and drawn. Fourth, based on Top-down design idea, pipeline control module with parallel and serial structure, fixed-point operation, the time sequences of the control signals are analyzed. Finally, the performance of FPGA-based system structure of LMS algorithm in time sequence and function is synthesized and simulated on Quartus II 4.1 platform and Stratix II family, and the research results show that it is feasible to implement adaptive filter using FPGA.