Integration of an STBus Type 3 protocol custom component into a HLS tool

Interface Synthesis in High-Level Synthesis (HLS) tool is the process by which it creates hardware interfaces from the formal C++ arguments of the C++ function being synthesized. The synthesis step uses size information from the C++ types along with user constraints and the interface components available in the libraries in order to identify the resources that can meet the user´s constraints. During scheduling, the appropriate quantity of interface resources will be allocated and inserted into the resulting RTL netlist generated by the HLS tool. Interface Synthesis components can be simple wires, basic protocol req/ack like, or more sophisticated bus-protocol (masters and/or slaves). This work describes the design and the integration of a custom 10 component implementing STMicroelectronics proprietary STBus Type 3 protocol. STBus is a set of protocols, interfaces, primitives and architectures specifying an interconnect subsystem, versatile in terms of performance, architecture and implementation. The STBus includes heavy-pipelined transactions and out- of-order management.