A wide-range and fixed latency of one clock cycle delay-locked loop

A wide-range delay-locked loop (DLL) with a fixed latency of one clock cycle is proposed. The phase selection circuit and the start-controlled circuit are used for this DLL to enlarge the operating frequency range and eliminate the harmonic locking problems. The operating frequency range of the DLL can be from 1/T_Dmin to 1/(N×T_Dmax), where T_Dmin and T_Dmax are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line theoretically. The prototype chip is fabricated in a 0.35-um 1P3M CMOS process. The measurement results exhibit the proposed DLL can operate from 6 MHz to 130 MHz and the latency of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter doesn´t exceed 25 ps. The DLL occupies an active area of 880-um×515-um and consumes a maximum power of 132 mW at 130 MHz