The transistor-level fault-tolerant design under changeful temperatures

In the real-world applications, many environment factors are unknown. Temperature is a considerable one of those factors because electronic systems´ performance can be significantly influenced by their working temperatures. Nowadays, existing researches on the robustness of the system are mainly focusing on extreme temperatures. However, for many real applications, the working temperatures could be variable. So it is significant to consider the system´s stability at unknown temperatures. This paper provides an algorithm to evolve gate-logic circuit which has better fault-tolerant performance under changeful temperatures. The diversifying strategy and fault-tolerant evaluating strategy are introduced. Experimental results demonstrate that, the NOT gate provided by this paper can work normal in a largest temperature range from −200°C to 200°C. Meanwhile, we can infer from the random temperature experiment that, the proposed circuit has better performance compared to conventional NOT gate.