A wide-linear-range subthreshold CMOS transconductor employing the back-gate effect

We present a CMOS circuit that utilizes the back-gate effect to extend the linear range of a subthreshold MOS transconductor. Previous designs of wide-linear-range transconductors using bipolar transistors employed multiple differential pairs with input offset voltages used to shift the individual transfer functions. These voltages were chosen to maximize the linear range of the summed differential pair currents. Equivalent offset voltages were generated by sizing emitter areas appropriately. Similar techniques may be applied to MOS circuits by scaling W/L ratios, but transistor size increases exponentially as we extend the linear range by adding more differential pairs. We introduce a method of adding equivalent offset voltages by biasing the back gate (i.e., body) of well devices appropriately. Test circuits built in a standard 0.5 μm CMOS process and using few transistors exhibit improved linear range over standard single-differential-pair transconductors.